Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Some other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
One type of function frequently implemented in a PLD is a Digital Signal Processing (DSP) function. DSP functions can include, for example, adders, subtractors, multipliers, and so forth. DSP circuits are commonly implemented using dedicated DSP logic blocks, hard-coded blocks included in a PLD for the specific purpose of efficiently implementing DSP functions. However, a hard-coded DSP function block necessarily has a predetermined width, e.g., 48 bits. When a 16-bit adder, for example, is implemented in a 48-bit DSP block, 32 bits of the DSP block are unused and go to waste. Also, some designs are DSP-intensive, and there may be some DSP functions that cannot be implemented in the DSP blocks simply because all available DSP blocks are already used to implement other DSP functions. Therefore, there are designs and/or design portions in which DSP functions can or must be implemented using the PLD fabric, e.g., in the CLB array.
In many PLD architectures, just a few DSP functions can consume a large amount of the available programmable logic resources. Clearly, the more efficiently these programmable logic resources are used, the more logic can be placed into the PLD. Alternatively, reducing the logic requirements of the DSP function or functions can allow a design to be implemented in a smaller and less expensive PLD. Therefore, it is clearly advantageous to provide efficient implementations of DSP functions such as adders and subtractors in the programmable fabric of a PLD.